Performance evaluation of MIC@R router for on-chip networks

Author

Ben-Tekaya, Rafik ; Baganne, Adel ; Torki, Kholdoun ; Tourki, Rached

Author_Institution

Electron. & Micro-Electron. Lab., Fac. of Sci. at Monastir, Monastir

fYear

2009

fDate

6-9 April 2009

Firstpage

97

Lastpage

101

Abstract

The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Proximity Hot-Spot Awareness (PHSA). The last scheme is a novel routing technique that improves better the latency and throughput compared to others schemes. The obtained results show that our router, combined with different routing algorithms has efficient performances.

Keywords

mesh generation; network routing; network-on-chip; 2D mesh networks; ASIC technology; adaptive routing algorithms; deterministic routing schemes; fully adaptive routing scheme; networks-on-chip design; on-chip networks; proximity congestion awareness routing scheme; proximity hot-spot awareness routing; router architecture; routing latency; Application specific integrated circuits; Buffer storage; Communication system control; Delay; Network-on-a-chip; Pipelines; Principal component analysis; Routing; Throughput; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on

Conference_Location

Cairo

Print_ISBN

978-1-4244-4320-8

Electronic_ISBN

978-1-4244-4321-5

Type

conf

DOI

10.1109/DTIS.2009.4938033

Filename

4938033