Design and implementation of a inter-chip bridge in a Multi-core SoC

Single-core DSP becomes more and more difficult to meet the demand of some application-specific fields, such as 3G mobile communication, consumer electronic systems and intelligent control devices. Recently, Multi-core DSP has received much concern and is believed to be an effective method to improve performance. QDSP is a multi-core DSP SoC developed by us. In this paper we present the design and implementation of the inter-chip asynchronous bridge in QDSP. An asynchronous FIFO is used to resolve multi-clock domain issue. The bridge has an area of 0.12 mum² in a 0.13 mum technology. Total area of inter-chip module is 0.65 mum², and valid bandwidth of data transmission is 1.63 Gb/s.