Design and implementation of a inter-chip bridge in a Multi-core SoC

Author

Yin, Yaming ; Chen, Shuming

Author_Institution

Dept. of Comput. Sci. & Tehnology, Nat. Univ. of Defense Technol., Changsha

fYear

2009

fDate

6-9 April 2009

Firstpage

102

Lastpage

106

Abstract

Single-core DSP becomes more and more difficult to meet the demand of some application-specific fields, such as 3G mobile communication, consumer electronic systems and intelligent control devices. Recently, Multi-core DSP has received much concern and is believed to be an effective method to improve performance. QDSP is a multi-core DSP SoC developed by us. In this paper we present the design and implementation of the inter-chip asynchronous bridge in QDSP. An asynchronous FIFO is used to resolve multi-clock domain issue. The bridge has an area of 0.12 mum² in a 0.13 mum technology. Total area of inter-chip module is 0.65 mum², and valid bandwidth of data transmission is 1.63 Gb/s.

Keywords

digital signal processing chips; integrated circuit design; system-on-chip; 3G mobile communication; QDSP; application-specific fields; asynchronous FIFO; bit rate 1.63 Gbit/s; consumer electronic systems; data transmission bandwidth; intelligent control devices; interchip asynchronous bridge; multiclock domain issue; multicore DSP SoC; size 0.13 mum; 3G mobile communication; Application software; Bridges; Consumer electronics; Data communication; Digital signal processing; Intelligent control; Multicore processing; Network-on-a-chip; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on

Conference_Location

Cairo

Print_ISBN

978-1-4244-4320-8

Electronic_ISBN

978-1-4244-4321-5

Type

conf

DOI

10.1109/DTIS.2009.4938034

Filename

4938034