Output response compaction in RAS-based schemes

Scan design has been the backbone of design for testability schemes in industry because it provides for controllability and observability of the internal flip flops of the circuit. However, the serial scan causes high switching activity during testing which results in high power dissipation. Another problem that may appear in scan designs is unknown values, which can invalidate the final signature captured in the response verifier. An alternate to serial scan architecture is random access scan (RAS). In RAS, flip-flops operate as addressable memory elements during test mode in a fashion similar to random access memory (RAM). This approach reduces the time needed to set and observe the states of the flip-flops while at the same time the power dissipation is reduced by as much as 99% comparatively to serial scan. In this work we propose a response compaction scheme for RAS- based architectures that results in lower hardware overhead compared to the response compaction scheme utilized in previous RAS-based schemes, while at the same time eliminates the problem of unknown values.