BRAM-based asynchronous FIFO in FPGA with optimized cycle latency

The design of BRAM-based FIFO in FPGA with high speed and low power consumption is presented. Meanwhile, the paper improves the design with optimized cycle latency to meet the requirements of instant and stability of state flag logic circuit design to support the high-performance FIFO. Moreover, two different types of address, B2G circuit and traveling-wave architecture accumulator are used to make the design with smaller area and lower power. Two more state flags are added to make it more practical to be controlled by users though expanding FIFO´s functions. And it shows 11.9% faster in frequency and only 28.8% of the area of FIFO in literature. The proposed FIFO can work with the same frequency as high performance Virtex-IV.