Power, delay and area efficient self-timed multiplexer and demultiplexer designs

Efficient gate level design methods for robust self-timed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.