Fast motion estimation algorithm and low-power CMOS motion estimation array LSI for MPEG-2 encoding

Author

Enomoto, Tadayoshi ; Sasajima, Yasumasa ; Hirobe, Atsunori ; Ohsawa, Tetsuya

Author_Institution

Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan

Volume

4

fYear

1999

fDate

36342

Firstpage

203

Abstract

For fast MPEG-2 encoding, a new motion estimation algorithm, called the “breaking-off-search” algorithm, was developed. The number of computations is drastically reduced by introducing computational constraints in a conventional full-search algorithm. Simulation results show that the “breaking-off-search” algorithm can reduce the computational complexity to about 40% of that for the full-search algorithm with a small loss of less than 0.02 dB in compression performance. This drastic reduction in the amount of block-matching computation can reduce power dissipation of a CMOS motion estimation array by a factor of about 15

Keywords

CMOS digital integrated circuits; computational complexity; data compression; low-power electronics; motion estimation; video coding; MPEG-2 encoding; array LSI; block-matching computation; breaking-off-search algorithm; compression performance; computational complexity; computational constraints; full-search algorithm; low-power CMOS; motion estimation algorithm; power dissipation; CMOS technology; Clocks; Computational complexity; Computational modeling; Encoding; Large scale integration; Motion estimation; Performance loss; Power dissipation; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.779977

Filename

779977