VIP: an FPGA-based processor for image processing and neural networks

Author

Cloutier, Jocelyn ; Cosatto, Eric ; Pigeon, Steven ; Boyer, François R. ; Simard, Patrice Y.

Author_Institution

Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada

fYear

1996

fDate

12-14 Feb 1996

Firstpage

330

Lastpage

336

Abstract

The present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture, together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm

Keywords

convolution; field programmable gate arrays; image processing; image processing equipment; multiprocessing systems; neural net architecture; optical character recognition; parallel architectures; pattern recognition equipment; 2D torus connection topology; FPGA-based processor; OCR; SIMD architecture; SIMD multiprocessor; VIP board; Virtual Image Processor; image processing; neural network algorithms; optimal hardware dedication; pattern recognition; Circuit topology; Communication system control; Field programmable gate arrays; Image processing; Image recognition; Network topology; Neural network hardware; Neural networks; Pattern recognition; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on

Conference_Location

Lausanne

ISSN

1086-1947

Print_ISBN

0-8186-7373-7

Type

conf

DOI

10.1109/MNNFS.1996.493811

Filename

493811