VLSI architecture and design for high performance adaptive video scaling

Author

Raghupathy, Arun ; Hsu, Pohsiang ; Liu, K. J Ray ; Chandrachoodan, Nitin

Author_Institution

Qualcomm. Inc., San Diego, CA, USA

Volume

4

fYear

1999

fDate

36342

Firstpage

406

Abstract

In this paper, we develop an efficient architecture for video scaling based on the adaptive image scaling algorithm. We then develop the design of the computation units and perform synthesis to show that the chip area required to perform scaling from QCIF to 4CIF is about 20 mm² using 0.5 μm technology

Keywords

VLSI; adaptive signal processing; application specific integrated circuits; data flow graphs; digital signal processing chips; interpolation; parallel architectures; pipeline processing; video signal processing; 0.5 micron; 20 mm; ASIC area requirements; CORDIC; Sobel block; VLSI architecture; Verilog; adaptive image scaling algorithm; bilinear interpolation; computation units design; data flow graph; efficient architecture; high performance adaptive video scaling; histogram-like computation; orientation angle; pipelining; required chip area; synthesis; Bandwidth; Computer architecture; Computer displays; Filtering; Filters; Flow graphs; Image resolution; Interpolation; Pixel; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780028

Filename

780028