DocumentCode
3422119
Title
Advanced alterable pipeline timer (adapt): a tool to design a high performance PowerPCTM microprocessor
Author
Burgess, Bradley G. ; Litch, Suzanne Plummer
Author_Institution
Somerset Design Center, Motorola Inc., Austin, TX, USA
fYear
1997
fDate
5-7 Feb 1997
Firstpage
271
Lastpage
276
Abstract
The microprocessor discussed in this paper is a member of the G3 family of PowerPC processors, the third generation of PowerPC microprocessor products. It provides the performance levels required for high end desktop systems while offering the low typical power dissipation and small die size that make it very attractive for portable systems. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated “backside” L2 cache. Most notably it achieves workstation/server class performance while only dissipating 5 watts. A major portion of the design effort involved architectural performance modeling, making cost/power/performance trade-offs, and verifying performance of the implementation
Keywords
microprocessor chips; performance evaluation; pipeline processing; G3 family; L2 cache; advanced alterable pipeline timer; architectural performance modeling; high performance PowerPC microprocessor; low typical power dissipation; out-of-order instruction execution; performance; performance levels; small die size; superscalar design; upstream branch processing; Costs; Energy management; Microarchitecture; Microprocessors; Monitoring; Performance analysis; Pipelines; Power dissipation; Process design; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International
Conference_Location
Phoenix, Tempe, AZ
Print_ISBN
0-7803-3873-1
Type
conf
DOI
10.1109/PCCC.1997.581527
Filename
581527
Link To Document