Title :
Testing sequential ILA´s
Author_Institution :
Craiova Univ., Romania
Abstract :
Sequential iterative logic arrays (ILAs) are studied with respect to two problems. First, some sufficient conditions are presented, which, when met, guarantee an upper bound on the size of the test set for the ILA under consideration. Second, procedures are presented for optimally testing and designing ILAs. The arrays are more general than those reported by other researchers and include bilateral and bidimensional arrays of a tetraconnected sequential Mealy-type machine. Octagonally and hexagonally connected arrays also are discussed. The results are very useful for image processing systems
Keywords :
image processing; integrated circuit testing; logic arrays; optimisation; ILAs; design; image processing; optimisation; sequential iterative logic arrays; testing; tetraconnected sequential Mealy-type machine; upper bound; Circuit faults; Circuit testing; Fault detection; Image processing; Integrated circuit interconnections; Logic arrays; Logic testing; Sequential analysis; System testing; Upper bound;
Conference_Titel :
Industrial Electronics, Control, Instrumentation, and Automation, 1992. Power Electronics and Motion Control., Proceedings of the 1992 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0582-5
DOI :
10.1109/IECON.1992.254472