DocumentCode :
3422775
Title :
3GSps Track-and-Hold circuit in 0.18 µ m CMOS process
Author :
Tang Kai ; Meng Qiao ; Liu Haitao ; Zhang Yi
Author_Institution :
Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China
fYear :
2011
fDate :
2-4 Aug. 2011
Firstpage :
323
Lastpage :
326
Abstract :
High-speed CMOS Track-and-Hold (T&H) circuit is the key component in the high-speed Analog-to-Digital converter (ADC). It is difficult to implementation GSps T&H in 0.18μm CMOS because of the bandwidth limitation in the OPA. In this paper, a 3GSps open loop T&H circuit in 0.18μm CMOS technology is proposed. The distortions in track mode and injection charge error in the hold mode were analyzed. CMOS switch and a differential buffer are used to trade off the speed, accuracy and sensitivity. Simulation results show that setup time, aperture time, aperture error and voltage drop rate are 280ps, 23ps, less than 3ps and 0.9μV/μs respectively. The T&H can work up to 3GHz at 1.8V supply and it could be used in 3GSps flash ADC in 0.18μm CMOS process.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; buffer circuits; sample and hold circuits; switches; 3GSps open loop T&H circuit; 3GSps track-and-hold circuit; CMOS switch; bandwidth limitation; differential buffer; high-speed CMOS track-and-hold circuit; high-speed analog-to-digital converter; size 0.18 mum; CMOS integrated circuits; CMOS technology; Capacitors; Irrigation; Noise; Silicon; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Technologies for Communications (ATC), 2011 International Conference on
Conference_Location :
Da Nang
ISSN :
2162-1020
Print_ISBN :
978-1-4577-1206-7
Type :
conf
DOI :
10.1109/ATC.2011.6027496
Filename :
6027496
Link To Document :
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