Differential 0.35 μm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications

Author

Djahanshahi, H. ; Salama, C.A.T.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

2

fYear

1999

fDate

36342

Firstpage

93

Abstract

Fully-differential CMOS circuits are presented for high speed Clock and Data Recovery (CDR) applications. The design is part of an integrated physical layer controller for an OC-12 ATM system, but can be used in other systems operating in 622 MHz-933 MHz range. Building blocks are presented including novel designs for VCO and charge pump. Two chips are implemented in 0.35 μm CMOS. One contains partitioned building blocks of a PLL-based CDR that, together with an external loop filter, can be used for flexible testing and application at a desired frequency. The other chip is a monolithic CDR with integrated loop filter particularly designed for application on 622 Mb/s NRZ data

Keywords

CMOS integrated circuits; UHF integrated circuits; asynchronous transfer mode; data communication equipment; high-speed integrated circuits; mixed analogue-digital integrated circuits; synchronisation; timing circuits; 0.35 micron; 622 Mbit/s; 622 to 933 MHz; NRZ data; OC-12 ATM system; PLL-based CDR; VCO; charge pump; differential CMOS circuits; high speed clock/data recovery; integrated loop filter; integrated physical layer controller; monolithic clock recovery applications; monolithic data recovery applications; Charge pumps; Circuits; Clocks; Control systems; Filters; Frequency; Optical signal processing; Physical layer; Testing; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780627

Filename

780627