Design of a transistor-mismatch-insensitive switched-current memory cell

Author

Wang, Chunyan ; Ahmad, M. Omair ; Swamy, M.N.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

2

fYear

1999

fDate

36342

Firstpage

105

Abstract

In this paper, we present a new and efficient switched-current memory cell consisting of six MOS transistors. A charge re-adjusting procedure is implemented in the memory cell to ensure an acceptable processing accuracy. Functionally, the current memory is insensitive to transistor parameter mismatch. The cell is currently under fabrication using 1.5-μm p-well single-poly technology with an area of about 50×25 μm². Applications of the proposed memory cell for the design of a multi-purpose analog signal processing operator are also discussed

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; analogue storage; integrated circuit design; switched current circuits; 1.5 micron; SI memory cell; analog signal processing operator; charge re-adjusting procedure; p-well single-poly technology; six MOS transistor configuration; switched-current memory cell; transistor-mismatch-insensitive memory cell; Current mode circuits; Fabrication; MOS capacitors; MOSFETs; Signal design; Signal processing; Switches; Transistors; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780630

Filename

780630