• DocumentCode
    3423881
  • Title

    The architecture of massively parallel processor CP-PACS

  • Author

    Boku, Taisuke ; Nakamura, Hiroshi ; Nakazawa, Kisaburo ; Iwasaki, Yoichi

  • Author_Institution
    Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
  • fYear
    1997
  • fDate
    17-21 Mar 1997
  • Firstpage
    31
  • Lastpage
    40
  • Abstract
    CP-PACS (Computational Physics by Parallel Array Computer System) is a massively parallel processor with 2048 processing units, built at the Center for Computational Physics, University of Tsukuba, Japan. The node processor of CP-PACS is a RISC microprocessor enhanced by pseudo vector processing, which can realize high performance vector processing. The interconnection network is the 3 dimensional Hyper-Crossbar Network, which has high flexibility and embeddability for various network topologies and communication patterns. The theoretical peak performance of the whole system is 614.4 GFLOPS. We present an overview of the CP-PACS architecture and several special architectural characteristics of it. A performance evaluation on the parallel LINPACK benchmark is also shown
  • Keywords
    multiprocessor interconnection networks; parallel architectures; parallel machines; performance evaluation; physics; physics computing; vector processor systems; 3 dimensional Hyper-Crossbar Network; Computational Physics by Parallel Array Computer System; RISC microprocessor; communication patterns; embeddability; high performance vector processing; interconnection network; massively parallel processor CP-PACS; massively parallel processor architecture; network topologies; node processor; parallel LINPACK benchmark; performance evaluation; processing units; pseudo vector processing; special architectural characteristics; Computer architecture; Computer science education; Concurrent computing; Information science; Microprocessors; Network topology; Physics computing; Quantum computing; Reduced instruction set computing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Algorithms/Architecture Synthesis, 1997. Proceedings., Second Aizu International Symposium
  • Conference_Location
    Aizu-Wakamatsu
  • Print_ISBN
    0-8186-7870-4
  • Type

    conf

  • DOI
    10.1109/AISPAS.1997.581622
  • Filename
    581622