New approach to and implementation of an LSI for high-speed image labeling

A single accelerator LSI chip for image labeling is presented, and an algorithm for primary labeling suitable for hardware implementation is proposed. The algorithm determines primary labels by using a simple 2×2 head window. The labeling LSI performs all labeling processes, including primary labeling, labeling unification, and secondary labeling. It runs at 40 MHz and can generate up to 4094 primary labels for handling both 4-point and 8-point connectivity