Transmit and receive digital filters subject to hardware cost constraints

Author

Fox, T.W. ; Carreira, A. ; Turner, L.E.

Author_Institution

Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada

Volume

2

fYear

2002

fDate

3-6 Nov. 2002

Firstpage

1055

Abstract

A method for the design of field programmable gate array (FPGA) based bit-serial Finite duration impulse response (FIR) transmit and receive digital filters is presented. Transmit and receive digital filters can be designed with near zero inter-symbol interference (ISI) and a specified normalized minimum stopband attenuation while using a specified number of logic elements (LEs). A tradeoff between the ISI and the hardware cost (the number of required LEs) is explored. It is shown that it is possible to obtain low cost transmit and receive digital filters at the expense of higher ISI.

Keywords

FIR filters; digital filters; field programmable gate arrays; intersymbol interference; network synthesis; receivers; transmitters; FPGA; ISI; bit-serial FIR digital filters; field programmable gate array; finite impulse response filters; hardware cost constraints; inter-symbol interference; logic elements; low cost digital filters; normalized minimum stopband attenuation; receive digital filter; transmit digital filter; Attenuation; Costs; Design methodology; Digital filters; Field programmable gate arrays; Finite impulse response filter; Hardware; Interference constraints; Intersymbol interference; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7576-9

Type

conf

DOI

10.1109/ACSSC.2002.1196945

Filename

1196945