DocumentCode
3423919
Title
Design of Min-Sum-based LDPC decoders using imprecise arithmetic
Author
Ngassa, Christiane L. Kameni ; Savin, Valentin ; Declercq, David
Author_Institution
CEA-LETI, Grenoble, France
fYear
2013
fDate
1-4 July 2013
Firstpage
375
Lastpage
382
Abstract
This work evaluates the robustness of Low-Density Parity-Check decoders against errors due to imprecise arithmetic. While the use of imprecise arithmetic is motivated by savings in energy, delay and area, it also causes errors during the decoding process. This is a new paradigm in coding theory, which traditionally assumes that an error correction decoder operates on exact hardware and errors can only be introduced by the transmission channel. We design imprecise arithmetic operators and investigate their use within several Min-Sum-based decoders. We show that all decoders are able to provide error protection, but most of them suffer a performance penalty compared to the exact arithmetic implementation. Remarkably, the Self-Corrected Min-Sum decoder incurs no performance penalty when imprecise arithmetic is used.
Keywords
digital arithmetic; error correction codes; parity check codes; coding theory; decoding process; error correction decoder; error protection; imprecise arithmetic operators; low-density parity-check decoders; min-sum-based LDPC decoder design; self-corrected min-sum decoder; transmission channel; Adders; Computer architecture; Decoding; Iterative decoding; Logic gates; Microprocessors; Fault-tolerance; LDPC codes; Min-Sum-based decoders; imprecise arithmetic; low-power decoders;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROCON, 2013 IEEE
Conference_Location
Zagreb
Print_ISBN
978-1-4673-2230-0
Type
conf
DOI
10.1109/EUROCON.2013.6625011
Filename
6625011
Link To Document