Title :
A high performance 0.25 /spl mu/m logic technology optimized for 1.8 V operation
Author :
Bohr, M. ; Ahmed, S.S. ; Ahmed, S.U. ; Bost, M. ; Ghani, T. ; Greason, J. ; Hainsey, R. ; Jan, C. ; Packan, P. ; Sivakumar, S. ; Thompson, S. ; Tsai, J. ; Yang, S.
Author_Institution :
Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
A 0.25 /spl mu/m generation logic technology has been developed with high performance transistors and five layers of planarized interconnect. The transistors are optimized for 1.8 V operation to provide high performance, low power and good reliability. The interconnects feature extensive use of planarization and high aspect ratio metal lines. 4 Mbit SRAMs with a 10.26 /spl mu/m/sup 2/ 6-T cell size have been built on this technology.
Keywords :
SRAM chips; integrated circuit interconnections; integrated circuit technology; integrated logic circuits; 0.25 micron; 1.8 V; 4 Mbit; 6-T cell; SRAM; aspect ratio; logic technology; low power operation; metal line; multilayer interconnect; optimization; planarization; reliability; transistor; Delay estimation; Isolation technology; Logic; MOSFETs; Maintenance; Measurement; Microprocessors; Planarization; Transistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.554112
