DocumentCode
3424018
Title
The design and implementation of Signal Integrity test vector generation based on JTAG
Author
Xuelong, Yan ; Hu Hejuan ; Haihui, Li
Author_Institution
Sch. of Electron. Eng., GUET, Guilin, China
fYear
2010
fDate
22-24 Oct. 2010
Firstpage
330
Lastpage
333
Abstract
With intensive study on IEEE std1149.1, and the basic idea of HTF(Half Transition) Fault Mode, an architecture for SI(Signal Integrity) test vector based on extended JTAG is designed and realized. The implementation of the idea is that, The advantage of the new instruction is that on the base of fully complied with IEEE1149.1 standard, it have been added to extend the function of boundary-scan architecture and provide the support to SI testing.
Keywords
IEEE standards; automatic test pattern generation; boundary scan testing; fault simulation; IEEE std1149.1; IEEE1149.1 standard; boundary-scan architecture; extended JTAG; half transition fault mode; signal integrity test vector generation; Computer crashes; BSC; HTF; IEEE1149.1; PGBSC; SI;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Computing and Integrated Systems (ICISS), 2010 International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-6834-8
Type
conf
DOI
10.1109/ICISS.2010.5656962
Filename
5656962
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