Title :
Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers
Author :
Shi, Bo ; Sundstrom, Lars
Author_Institution :
Dept. of Appl. Electron., Lund Univ., Sweden
Abstract :
This paper describes an integrated circuit design and implementation of a simple and partly new RF power amplifier linearization system based on power feedback. The prototype linearization IC using a standard double-metal double-poly 0.8 μm CMOS process was fabricated and tested. When it was used to linearize an efficient power amplifier transmitting a π/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal, experimental results showed that a reduction of more than 10 dB in the adjacent channel interference was achieved. The chip, which occupies 1.9 mm2 with pads, operates with 5 V supply voltage and measured power consumption is 65 mW
Keywords :
CMOS analogue integrated circuits; adjacent channel interference; cellular radio; feedback amplifiers; integrated circuit design; interference suppression; linearisation techniques; power amplifiers; power integrated circuits; radiofrequency amplifiers; π/4-shifted DQPSK modulated NADC signal; 0.8 micron; 5 V; 65 mW; ACI reduction; CMOS power feedback linearization IC; RF power amplifiers; adjacent channel interference; double-metal double-poly CMOS process; integrated circuit design; power amplifier linearization system; CMOS integrated circuits; CMOS process; Circuit testing; Feedback; Integrated circuit synthesis; Power amplifiers; Prototypes; Radio frequency; Radiofrequency amplifiers; Radiofrequency integrated circuits;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780688
