An Efficient 64-point Pipelined FFT Engine

The Fast Fourier Transform (FFT) is a very important algorithm in signal processing, software defined radio and the most promising modulation technique i.e. Orthogonal Frequency Division Multiplexing (OFDM). This paper describes the design and implementation of a fully pipelined 64-point FFT engine in programmable logic. The FFT takes 16-bit fixed point complex numbers as input and after a known pipelined latency of 20 clock cycles produces the desired output. The input data samples are fed in parallel to the FFT engine to generate outputs in parallel. The architecture is capable of performing FFT operation without changing the internal coefficients which makes it highly suitable for practical applications. The architecture requires 25% multiplication operations compared to conventional Cooley-Tukey approach. Hence it leads to low power and area saving.