Virtual prototyping of a Wafer Level Chip Scale Package: Underfill role in die cracking

With the increased complexity of SiP (system in package), Finite Element simulations take an important role in predicting the thermo-mechanical package reliability. Failures in flip chip packages such as die cracking and fatigue of solder bumps are specially the result of the mismatch in thermal expansion coefficients between die and the substrate. In some packages, we use an underfill to improve the reliability of the flip chip by reducing stress in the die and in bumps. But the choice of the underfill depends on the application. Using simulations allows us to better choose the right underfill. To perform this virtual prototyping, a methodology is followed and described. This paper highlights the effect of underfill on die cracking at Wafer Level Chip Scale Package (WLCSP) and exhibits ways to prevent this failure. The package analyzed is a WLCSP SiP composed by three active chips flipped on an Integrated Passive Die (IPD) and all assembled on a flex using lead-free solder bumps. Various kinds of underfill are tested in this assembly. The underfill used has a significant role in the fracture of the die.