A digital technique for reducing clock jitter effects in time-interleaved A/D converter

Time-interleaved A/D converter is an effective approach to increase the data throughput. However, it suffers from clock jitter existing in the multi-phase clocks, which degrade the converter´s Spurious-Free-Dynamic-Range (SFDR) as well as the Signal-to-Noise Ratio (SNR). In this paper, a digital technique is proposed to reduce these non-ideal effects by obtaining a better estimation on the output data through the use of interpolation. Simulation results show that the proposed technique significantly improves the SFDR by 20~50 dB