Title :
Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment-matching
Author :
Chen, Chung-Ping ; Menezes, Noel
Author_Institution :
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric a noise-aware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results
Keywords :
circuit optimisation; circuit simulation; integrated circuit design; integrated circuit interconnections; method of moments; wiring; attackers; circuit simulation results; hierarchical moment-matching; interconnect optimization; linear time; noise-aware repeater insertion; on-chip interconnect; wire segments; wire sizing; Algorithm design and analysis; Delay effects; Delay estimation; Design automation; Design optimization; Driver circuits; Integrated circuit interconnections; Permission; Repeaters; Wire;
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
DOI :
10.1109/DAC.1999.781367