The architecture, logic, and circuit design of a bipolar, 200 Mbyte/sec, serializing data mover IC, with 32-bit TTL-compatible parallel I/O and unique 1.8 Gbit/sec `cutoff driver´ differential PECL serial I/O

Author

Jeffery, Phil ; Ford, David ; Pham, Phuc ; Reed, Mike ; Srinivasan, Naridini ; Weir, Bernie

Author_Institution

Div. of Logic Integrated Circuits, Motorola Inc., Chandler, AZ, USA

fYear

1995

fDate

2-3 Oct 1995

Firstpage

51

Lastpage

54

Abstract

This paper discusses the architecture, logic design, and circuit design of the Autobahn Spanceiver-a serializing transceiver IC that facilitates movement of arbitrarily large blocks of 32-bit parallel TTL data at data rates up to 200 MBytes/sec, between two or more nodes on a shared, controlled-impedance, half-duplex, 1.8 Gbit/sec, differential-PECL serial channel

Keywords

bipolar digital integrated circuits; data communication; data communication equipment; digital communication; integrated circuit design; logic design; system buses; transceivers; 1.8 Gbit/s; 200 Mbyte/s; 32 bit; 32-bit parallel TTL data; Autobahn Spanceiver; TTL-compatible parallel I/O; circuit design; computer backplanes; cutoff driver; differential PECL serial I/O; half-duplex channel; logic design; serializing data mover IC; serializing transceiver IC; Bipolar integrated circuits; Circuit synthesis; Clocks; Computer architecture; Driver circuits; Impedance; Logic circuits; Logic design; Synchronization; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-2778-0

Type

conf

DOI

10.1109/BIPOL.1995.493864

Filename

493864