Title :
A new BIST solution for system-on-chip
Author :
Ling, Zhang ; Jishun, Kuang
Author_Institution :
Coll. of Comput. & Commun., Hunan Univ., China
Abstract :
The paper presents a new solution to the test of core-based systems based on the low-power BIST scheme. Cores in the system are divided into several groups. Each group has a BIST scheme. The cores in the same group share the low-power BIST that consists of a LFSR and a mapping logic, and the cores are tested in sequence. The cores not in the same group are tested concurrently. The target of the solution is to minimize the test time under the power constraint. Simulative experimental results show that our solution saves a significant amount of test time under the power constraint, and the hardware overhead is not high.
Keywords :
built-in self test; cores; integrated circuit testing; logic testing; low-power electronics; system-on-chip; LFSR; core based system testing; low-power BIST; mapping logic; system-on-chip; Built-in self-test; Costs; Educational institutions; Hardware; Logic testing; Microelectronics; Scheduling; Silicon; System testing; System-on-a-chip;
Conference_Titel :
Dependable Computing, 2005. Proceedings. 11th Pacific Rim International Symposium on
Print_ISBN :
0-7695-2492-3
DOI :
10.1109/PRDC.2005.9
