Low Complexity Out-of-Order Issue Logic Using Static Circuits

Author

Mhambrey, S.S. ; Maurya, Sanjay Kumar ; Clark, Lawrence T.

Author_Institution

Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA

Volume

21

Issue

2

fYear

2013

fDate

Feb. 2013

Firstpage

380

Lastpage

384

Abstract

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.

Keywords

CMOS logic circuits; logic circuits; logic design; silicon-on-insulator; SOI; Si; fully static CMOS circuits; low complexity out-of-order issue logic; single-cycle issue queue circuit architecture; size 45 nm; static circuits; CMOS integrated circuits; Clocks; Complexity theory; Computer aided manufacturing; Logic gates; Multiplexing; Out of order; CMOS digital integrated circuit; issue queue; microprocessor; out-of-order instruction issue; superscalar;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2012.2184310

Filename

6144734