• DocumentCode
    3426439
  • Title

    Design of defect tolerant Wallace multiplier

  • Author

    Namba, Kazuteru ; Ito, Hideo

  • Author_Institution
    Fac. of Eng., Chiba Univ., Japan
  • fYear
    2005
  • fDate
    12-14 Dec. 2005
  • Abstract
    This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the proposed design is also shown. This paper evaluates the proposed design from the view point of the yield, area and delay time. For example, the yield of a 32 × 32 Wallace multiplier increases from 0.90 to 0.99 by applying the proposed design while the area increases by a factor of 1.89.
  • Keywords
    fault tolerance; integrated circuit yield; logic design; multiplying circuits; bit-slice reconfiguration redundant design; defect tolerant Wallace multiplier design; Adders; Circuit faults; Communication cables; Data processing; Delay effects; Joining processes; Logic circuits; Reconfigurable logic; Tree data structures; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Computing, 2005. Proceedings. 11th Pacific Rim International Symposium on
  • Print_ISBN
    0-7695-2492-3
  • Type

    conf

  • DOI
    10.1109/PRDC.2005.30
  • Filename
    1607529
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3426439