Design of defect tolerant Wallace multiplier

This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the proposed design is also shown. This paper evaluates the proposed design from the view point of the yield, area and delay time. For example, the yield of a 32 × 32 Wallace multiplier increases from 0.90 to 0.99 by applying the proposed design while the area increases by a factor of 1.89.