Multimedia SoC: a systolic core for embedded DCT evaluation

Author

Cariccia, F. ; Cariccia, P. ; Martina, M. ; Molino, A. ; Vacca, F.

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

Volume

2

fYear

2002

fDate

3-6 Nov. 2002

Firstpage

1749

Abstract

The growing interest in video standards has fostered many research activities towards efficient transform architectures. Many works have been proposed concerning the discrete cosine transform (DCT); however the need is felt for efficient cores, ready to be embedded into systems on chip (SoC). To grant maximal interoperability among different cores, the proposed DCT one has been designed to be wishbone compliant. A reconfigurable systolic 2D-DCT architecture is proposed and physical implementation results on XILINX Virtex-E FPGA are given. As far as performance is concerned, this core is able to process 128 XGA (1024/spl times/768) frames/s running at 110 MHz.

Keywords

discrete cosine transforms; embedded systems; field programmable gate arrays; logic design; multimedia computing; system-on-chip; systolic arrays; video coding; 1024 pixel; 110 MHz; 768 pixel; XGA; XILINX Virtex-E FPGA; discrete cosine transform; embedded DCT; multimedia SoC; system on chip; systolic 2D-DCT architecture; systolic core; transform architectures; video coding; video standards; wishbone compliant; Clocks; Communication standards; Discrete cosine transforms; Discrete transforms; Field programmable gate arrays; Hardware; Multimedia communication; Radio communication; System-on-a-chip; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7576-9

Type

conf

DOI

10.1109/ACSSC.2002.1197075

Filename

1197075