PROPTEST: a property based test pattern generator for sequential circuits using test compaction

Author

Guo, Ruifeng ; Reddy, Sudhakar M. ; Pomeranz, Irith

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1999

fDate

1999

Firstpage

653

Lastpage

659

Abstract

We describe a property based test generation procedure that uses static compaction to generate test sequences that achieve high fault coverages at a low computational complexity. A class of test compaction procedures are proposed and used in the property based test generator. Experimental results indicate that these compaction procedures can be used to implement the proposed test generator to achieve high fault coverage with relatively smaller run times

Keywords

automatic test pattern generation; circuit analysis computing; computational complexity; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; PROPTEST; high fault coverages; low computational complexity; property based test pattern generator; sequential circuits; static compaction; test compaction; test sequences; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Logic testing; Permission; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings. 36th

Conference_Location

New Orleans, LA

Print_ISBN

1-58113-092-9

Type

conf

DOI

10.1109/DAC.1999.782023

Filename

782023