Right-half-plane zero removal technique for low-voltage low-power nested Miller compensation CMOS amplifier

Author

Leung, Ku Nuizg ; Mok, Philip K T ; Ki, Wing-Hung

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong

Volume

2

fYear

1999

fDate

5-8 Sep 1999

Firstpage

599

Abstract

The stability of a low-power CMOS three-stage nested Miller compensated (NMC) amplifier is deteriorated by a right-half-plane (RHP) zero. A technique using only one null resistor in the NMC amplifier to eliminate the RHP zero is developed. Both theory and experimental result show that the RHP zero is effectively eliminated by the proposed technique. The NMC amplifier using this technique has about 30% improvement in the bandwidth, slew rate and settling time with an improvement on the phase margin and no increase on the power consumption. Moreover, there is at least 49 dB enhancement on the negative power supply rejection ratio

Keywords

CMOS analogue integrated circuits; circuit stability; compensation; differential amplifiers; feedback amplifiers; integrated circuit design; linear network analysis; linear network synthesis; low-power electronics; poles and zeros; LV CMOS amplifier; amplifier stability; bandwidth; low-power operation; low-voltage operation; negative power supply rejection ratio; nested Miller compensation; null resistor; phase margin; right-half-plane zero removal technique; settling time; slew rate; three-stage configuration; Bandwidth; CMOS technology; Capacitors; Energy consumption; Frequency; Power amplifiers; Power supplies; Resistors; Stability; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.813179

Filename

813179