• DocumentCode
    3428093
  • Title

    A BiCMOS fully-differential 10-bit 40 MHz pipelined ADC

  • Author

    Shu, Tzi-Hsiung ; Bacrania, Kantilal ; Gokhale, Ravindra

  • Author_Institution
    Harris Semicond., Melbourne, FL, USA
  • fYear
    1995
  • fDate
    2-3 Oct 1995
  • Firstpage
    154
  • Lastpage
    157
  • Abstract
    A BiCMOS fully-differential, 10-bit, 40 MHz pipelined ADC has been developed. The ADC can digitize not only a fully-differential but also a single-ended signal over a wide input range with little variation in performance. At fs=40 MHz, the ADC exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW from a single 5-V supply
  • Keywords
    BiCMOS integrated circuits; analogue-digital conversion; pipeline processing; 10 bit; 40 MHz; 400 mW; 5 V; BiCMOS fully-differential pipelined ADC; digitization; signal-to-noise+distortion ratio; single-ended signal; Bandwidth; BiCMOS integrated circuits; CMOS process; Capacitors; Distortion; Energy consumption; Operational amplifiers; Sampling methods; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995
  • Conference_Location
    Minneapolis, MN
  • Print_ISBN
    0-7803-2778-0
  • Type

    conf

  • DOI
    10.1109/BIPOL.1995.493887
  • Filename
    493887
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3428093