Title :
On modeling and hardware implementation of Space-Time Adaptive Processing (STAP) for target detection in passive BI-static radar
Author :
Ul Mahmood, Z. ; Alam, M. ; Jamil, Khalid ; Elnamaky, M.
Author_Institution :
Dept. of Electr. Eng., King Saud Univ., Riyadh, Saudi Arabia
Abstract :
This paper presents the modeling and partial FPGA implementation of Space Time Adaptive Processing (STAP) algorithm for Passive Bi-static Radar (PBR) using commercial FM transmitter as illuminator of opportunity. Two simulated targets were inserted in the real-time recorded FM eight channel data signal. The simulated targets were detected after effective zero Doppler frequency clutter removal with the help of optimum matched filtering. Hardware implementation of STAP processor including phase correction, Doppler frequency correction and Kronecker product is provided and explained. The system was designed and developed using Xilinx FPGA Virtex-6 platform.
Keywords :
Doppler radar; field programmable gate arrays; filtering theory; matched filters; object detection; passive radar; radar clutter; radar signal processing; radar transmitters; space-time adaptive processing; Doppler frequency correction; Kronecker product; PBR; STAP processor; Xilinx FPGA Virtex-6 platform; commercial FM transmitter; hardware implementation; illuminator; optimum matched filtering; partial FPGA implementation; passive bistatic radar; phase correction; real-time recorded FM eight channel data signal; space-time adaptive processing; target detection; zero Doppler frequency clutter removal; Doppler effect; Field programmable gate arrays; Frequency modulation; Hardware; Radar; Vectors;
Conference_Titel :
Information Science, Signal Processing and their Applications (ISSPA), 2012 11th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0381-1
Electronic_ISBN :
978-1-4673-0380-4
DOI :
10.1109/ISSPA.2012.6310437
