Efficient drivers, receivers and repeaters for low power CMOS bus architectures

Author

Rjoub, A. ; Koufopavlou, O.

Author_Institution

Dept. of Electr. & Comput. Eng., Patras Univ., Greece

Volume

2

fYear

1999

fDate

5-8 Sep 1999

Firstpage

789

Abstract

New driver/receiver CMOS circuits design, for low-power VLSI applications, are proposed. They are based on the low swing technique. A significant reduction in power dissipation is achieved, due to the reduced swing voltage on the interconnection loads. Comparisons of the delay time of the proposed circuits with the conventional CMOS driver/receiver are presented. For different values of supply voltage, using 0.5 μm process technology, SPICE measurements show up to 27% improvement in the total driver/receiver power-delay product. Finally, circuits as repeaters are proposed for long interconnections

Keywords

CMOS digital integrated circuits; VLSI; delays; driver circuits; integrated circuit design; low-power electronics; receivers; repeaters; 0.5 micron; delay time; driver/receiver CMOS circuits design; drivers; interconnection loads; long interconnections; low power CMOS bus architectures; low swing technique; low-power VLSI applications; power dissipation; power-delay product; receivers; repeaters; CMOS technology; Circuit synthesis; Delay effects; Driver circuits; Integrated circuit interconnections; Power dissipation; Repeaters; SPICE; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.813227

Filename

813227