Title :
Design validation of .18 μm 1 GHz cache and register arrays
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
This paper describes the design and results of SRAM experiments from a prototype test chip in IBM´s .18 μm 7LM copper BEOL technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM´s S/390 L2 cache chips require multifaceted approaches to address the following: (i) SRAM operability in product-like clocking and ABIST environments. (ii) Demonstration of yield using 2-dimensional redundancy. (iii) Characterization of SRAM signals used in the macro timing rules. (iv) Obtain high volume pre-product manufacturing test experience. (v) Verify SRAM functionality at technology stress test conditions. Prototype test chips in IBM´s .18 μm technology have provided opportunities to investigate these areas, greatly mitigate risks associated with ever decreasing product design cycles and exercise the SRAM timing rules and logic models in a product-like application
Keywords :
SRAM chips; built-in self test; cache storage; environmental testing; integrated circuit design; production testing; redundancy; timing; 0.18 micron; 1 GHz; 2-dimensional redundancy; 7LM BEOL technology; ABIST environments; Cu; IBM S/390 L2 cache chips; SRAM experiments; cache arrays; logic models; macro timing rules; multifaceted approaches; pre-product manufacturing test experience; product applications; product cycle time; product-like clocking; register arrays; technology stress test conditions; timing rules; Clocks; Copper; Logic testing; Manufacturing; Product design; Prototypes; Random access memory; Registers; Stress; Timing;
Conference_Titel :
Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0259-8
DOI :
10.1109/MTDT.1999.782684
