A new algorithm and its VLSI architecture design for connected component labeling

The component labeling process basically consists of label-assigning and label-merging steps. Label-assigning step is to give a rough labeling number for each dotted pixel in a binary image and find the equivalent relations for all the labeling numbers. On the basis of these equivalent relations, the label-merging step is to merge these labeling numbers to give a unique number for a connected component. These two steps need immense logical computations and memory accesses, and hence restrict the feasibility of real-time applications. In this paper, we solve this problem through the design of a novel algorithm and VLSI architecture based on an 8-adjacent rule