Title :
Energy-efficient class AB CMOS Sample and Hold circuit
Author :
Lopez-Martin, Antonio J. ; Ugalde, Xabier ; Ramirez-Angulo, Jaime
Author_Institution :
Dept. of Electr. & Electron. Eng., Public Univ. of Navarra, Pamplona, Spain
Abstract :
A class AB Sample and Hold circuit is presented. Class AB operation allows achieving high slew rate with very low static power requirements. Measurement results of a test chip prototype in a 0.5-μm CMOS process demonstrate a settling time of 1.9 μs using a large load capacitance of 50 pF with only 81 μW of static power consumption. Silicon area is 0.075 mm2.
Keywords :
CMOS analogue integrated circuits; sample and hold circuits; capacitance 50 pF; class AB CMOS sample and hold circuit; class AB amplifiers; class AB operation; power 81 muW; time 1.9 mus; very low static power requirements; CMOS integrated circuits; Capacitance; Gain; Power demand; Topology; Transistors; Voltage measurement; Class AB amplifiers; SC circuits; analog CMOS design; low-power circuits; sample and hold circuits;
Conference_Titel :
EUROCON, 2013 IEEE
Conference_Location :
Zagreb
Print_ISBN :
978-1-4673-2230-0
DOI :
10.1109/EUROCON.2013.6625246
