Title :
A 150 mW, 155 MHz phase locked loop with low jitter VCO
Author :
McNeill, John ; Croughwell, Rosamaria ; DeVito, Lawrence ; Gasinov, A.
Author_Institution :
Boston Univ., MA, USA
fDate :
30 May-2 Jun 1994
Abstract :
This paper describes a 155 MHz clock recovery phase locked loop (PLL) for use in fiber optic serial data communication systems. The PLL incorporates a low jitter voltage controlled ring oscillator. Some of the inherent limitations of the ring architecture, as well as design techniques for dealing with those limitations, are discussed. The PLL chip has been fabricated in a dielectrically isolated complementary bipolar process, occupies a die area of 2 mm×3 mm, and consumes 150 mW operating from a 5V supply
Keywords :
bipolar digital integrated circuits; data communication equipment; digital phase locked loops; jitter; optical fibre communication; optical receivers; timing circuits; voltage-controlled oscillators; 150 mW; 155 MHz; 5 V; PLL chip; clock recovery PLL; complementary bipolar process; design techniques; dielectrically isolated process; fiber optic serial data communication; low jitter VCO; phase locked loop; ring architecture; voltage controlled ring oscillator; Clocks; Communication system control; Data communication; Jitter; Low voltage; Optical fibers; Phase locked loops; Ring oscillators; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409099
