The Logic Description Generator

The authors describe the Logic Description Generator (LDG), a design tool specifically geared to aid in the implementation of systolic algorithms on reconfigurable logic arrays. It is used to specify designs for Splash, a linear array of Xilinx chips. LDG supports the notion of a logical systolic cell, which may be repetitively layed out across a chip, and whose instances may be interconnected as a linear array. LDG also contains a reshape operator, which allows the hardware designer to place each component of the linear array at a specific location on the chip. Another feature of LDG is the ability to write general parameterized library routines. LDG allows the designer to make a simple change to a single cell and then have that change affect the configuration and layout of every other cell on the chip in a time frame comparable to the software edit-compile-test cycle. The turnaround time from textual chip specification to testing the new configuration on the Splash hardware is on the order of a half-hour, of which the LDG process contributes about five minutes. LDG is implemented in Common Lisp and runs in the Sun workstation environment. The LDG processor generates Xilinx Netlist format (XNF), which is a textual description of each logic element on the chip