Extensions to linear mapping for regular arrays with complex processing elements

The optimal architectural design of the processing elements (PEs) for an application specific regular array (RA) is nontrivial if the application has a complex operation set. The authors present an approach that extends the conventional, linear time-space transformation for such cases. In application-specific-integrated-circuit (ASIC) architectures, one has the freedom to fine-tune all aspects of the architecture to optimize the throughput. Therefore, the PEs can be designed to match the throughput and to optimize the area-cost of an RA architecture. The method presented allows a free design of the PEs with internal pipelining of the data paths, hardware sharing of operators among operations, multicycle operators, and interleaving of the execution of different index points. Compared to methods that allow only parts of these experiments, the local area-time tradeoffs are now explicitly incorporated in the global space-time assignment problem