Silicon dioxide as passivating, ultrathin layer in MOSFET gate stacks

Author

Bieniek, T. ; Wojtkiewicz, A. ; Lukasiak, L. ; Beck, R.B.

fYear

2001

fDate

26-30 June 2001

Firstpage

163

Lastpage

164

Abstract

Two different methods of ultrathin oxide formation are studied here, classical thermal oxidation and Grilox (see Borsoni et al., Microelectronics Reliability). It was proved that the quality of the passivating layer has a crucial influence on the overall properties of the gate stack in all cases, for the well established technology of Si/sub 3/N/sub 4/, as well as for HfO/sub 2/ (still under investigation). The interface trap density distributions in the Si forbidden gap for exemplary test devices are presented.

Keywords

MOSFET; dielectric thin films; electron traps; hole traps; interface states; oxidation; passivation; silicon compounds; Grilox; HfO/sub 2/; MOS IC technology; MOSFET gate stacks; Si; Si forbidden gap; Si-SiO/sub 2/-HfO/sub 2/; Si-SiO/sub 2/-Si/sub 3/N/sub 4/; Si/sub 3/N/sub 4/; SiO/sub 2/ ultrathin passivating layer; dielectric double layer; interface trap density distributions; thermal oxidation; ultrathin oxide formation; Capacitance; Dielectric constant; Dielectric materials; Dielectric substrates; Hafnium oxide; High-K gate dielectrics; MOSFET circuits; Microelectronics; Permittivity; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Wide Bandgap Layers, 2001. Abstract Book. 3rd International Conference on Novel Applications of

Conference_Location

Zakopane, Poland

Print_ISBN

0-7803-7136-4

Type

conf

DOI

10.1109/WBL.2001.946588

Filename

946588