DocumentCode :
3430106
Title :
Si single-electron MOS memory with nanoscale floating-gate and narrow channel
Author :
Langjie Guo ; Leobandung, E. ; Chou, S.Y.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
1996
fDate :
8-11 Dec. 1996
Firstpage :
955
Lastpage :
956
Abstract :
Floating-gate MOS memories based on single electron effect are very attractive, because of the potential quantized threshold voltage shift, quantized charging voltage to create the shift, small device size and fast charging time. However, to relax the challenges in fabricating such devices, previous single-electron MOS memories (SEMMs) had to have nonconventional structures (e.g. a polysilicon channel or a floating gate consisting of many isolated silicon nanocrystals), causing large fluctuation in device dimension and performance and making them unsuitable to ULSI. Here we present the first SEMMs having a narrow crystalline Si channel and a nanoscale poly-Si floating gate of a well controlled dimension. We report that charging of a single electron to the floating gate will lead to, at room temperature, quantized threshold voltage shift, discrete charging voltage, and self-limiting charging process.
Keywords :
MOS memory circuits; MOSFET; ULSI; elemental semiconductors; nanotechnology; silicon; single electron transistors; Si; ULSI; charging time; discrete charging voltage; nanoscale floating-gate; narrow channel; quantized charging voltage; quantized threshold voltage shift; self-limiting charging process; single-electron MOS memory; Electrons; Laboratories; Lithography; Nanocrystals; Nanoscale devices; Nonvolatile memory; Oxidation; Silicon; Threshold voltage; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Print_ISBN :
0-7803-3393-4
Type :
conf
DOI :
10.1109/IEDM.1996.554141
Filename :
554141
Link To Document :
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