• DocumentCode
    3430222
  • Title

    An improved multilayer neural model and array processor implementation

  • Author

    Chiang, C.C. ; Fu, H.C.

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    1990
  • fDate
    5-7 Sep 1990
  • Firstpage
    389
  • Lastpage
    400
  • Abstract
    The authors present a method for obtaining faster learning in a multilayer neural network. The key ingredient is the concept of floating positive/negative thresholds used in the output neurons to interpret the output states. In a traditional multilayer perceptron, the output state is 1 or 0, depending on whether the activation value exceeds the fixed target threshold or not. The proposed approach determines the state of an output activation by comparing the difference between the output activation and the two floating positive/negative thresholds. If the output activation is closer to the positive threshold or negative threshold, then the output state is 1 or 0 respectively. The iterative learning process completes whenever it is decided that an activation value is closer to its target threshold. Simulation results show that the learning iterations for the model are a hundred times fewer than for the traditional multilayer perceptron. Mapping this multilayer neural net onto a ring systolic array maximizes the strength of VLSI in terms of intensive and pipeline computing
  • Keywords
    iterative methods; learning systems; microprocessor chips; neural nets; parallel algorithms; parallel architectures; pipeline processing; systolic arrays; VLSI; array processor implementation; floating positive/negative thresholds; iterative learning process; multilayer neural model; output activation; pipeline computing; ring systolic array; Computational modeling; Computer science; Multi-layer neural network; Multilayer perceptrons; Neural networks; Neurons; Nonhomogeneous media; Pipelines; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Array Processors, 1990. Proceedings of the International Conference on
  • Conference_Location
    Princeton, NJ
  • Print_ISBN
    0-8186-9089-5
  • Type

    conf

  • DOI
    10.1109/ASAP.1990.145475
  • Filename
    145475