Fault-tolerant array processors using N-and-half-track switches

The author addresses the fault tolerance issue for rectangular arrays of a large number of processors. An array grid model based on n1/2-track switches is adopted. This model is a generalization of previous models using 1 1/2-track switches and 2 1/2-track switches. A reconfigurability theorem for n1/2 track arrays is established and a concept of pseudo processing elements (PEs) is introduced to decompose a routing problem into problems with smaller track numbers. Therefore, with the decomposition technique, only the routing algorithm developed for 1 1/2-track arrays is required. Simulation results for the 1 1/2-track array and 2 1/2-track array are given