DocumentCode
3430266
Title
Design of CML gate with the best propagation delay
Author
Alioto, M. ; Palumbo, G.
Author_Institution
Dipt. Elettrico, Elettronico e Sistemistico, Catania Univ., Italy
Volume
1
fYear
1998
fDate
1998
Firstpage
287
Abstract
In this paper a design strategy to optimize the propagation delay of CML gates is proposed. The strategy is also properly modified to reduce power dissipation with only 10% increase in the minimum propagation delay. The design is based on a simple, but efficient model which is validated with a 6 GHz and 20 GHz bipolar technologies
Keywords
bipolar logic circuits; current-mode logic; delay estimation; equivalent circuits; logic design; logic gates; 20 GHz; 6 GHz; CML gate design; bipolar technologies; design strategy; power dissipation reduction; propagation delay optimisation; Carbon capture and storage; Design optimization; Digital circuits; Frequency; Logic circuits; Parasitic capacitance; Power dissipation; Power system modeling; Propagation delay; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.813323
Filename
813323
Link To Document