Dynamic systolic associative memory chip

A dynamic random access memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (256×4096) associative memory chip based on a 1-Mb DRAM, the ~10 transistors per sense amplifier in a DRAM are expanded to ~24 transistors per sense amplifier in the modified chip. The chip size is only slightly increased, and it is manufactured using the same processes, in the same plant, as a DRAM chip; thus, it should cost about the same as a DRAM. A large array of such modified DRAMs could store a terabit database and search all of it every 60 μs. Bit pattern searching and search-rewrite algorithms could be economically performed over very large amounts of data. The concepts and the design of the simple modified DRAM are discussed