Title :
Designing specific systolic arrays with the API15C chip
Author :
Frison, P. ; Gautrin, E. ; Lavenier, D. ; Scharbarg, J.L.
Author_Institution :
IRISA, Rennes, France
Abstract :
The API15C processor, a building block for different systolic structures, is designed exclusively for single-instruction-multiple data (SIMD) execution mode. To support this mode, the instruction set includes special control instructions. Three parallel I/O ports are available for different interconnection schemes. The API15C chip is designed in a CMOS 2-μm technology. It contains 45000 transistors on a 6-mm $M6.2-mm silicon area. The functionality of the circuit was tested successfully after the first run. It executes one instruction per clock phase of 100 ns, giving a global rate of 10 MIPS. To validate this processing element as a building block for systolic structures, a programmable interface and two single board machines were developed. The first is an 18 processor linear structure able to support a wide range of applications. The second is a 28 processor bidimensional structure for a specific application of string comparison. The instruction set is particularly well-suited for SIMD operation
Keywords :
CMOS integrated circuits; VLSI; logic design; microprocessor chips; pipeline processing; systolic arrays; 10 MIPS; 2 micron; API15C processor; CMOS; SIMD operation; Si; building block; single-instruction-multiple data; systolic arrays; Array signal processing; Clocks; Computer architecture; Image processing; LAN interconnection; Parallel processing; Process design; Registers; Systolic arrays; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145486
