Title :
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Author :
Reed, I.S. ; Shih, M.T. ; Hendon, E. ; Truong, T.K. ; Tufts, D.W.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical fast Fourier transform (FFT) in terms of accuracy, complexity and speed. Theorems developed previously for the AFT algorithm are used to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A computationally balanced AFT algorithm for Fourier analysis and signal processing is developed. This algorithm does not require complex multiplications. A VLSI architecture is suggested for this amplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25% over that used by the direct method. This efficient AFT algorithm is shown to be identical to Brun´s original AFT algorithm
Keywords :
Fourier analysis; Fourier transforms; VLSI; computerised signal processing; digital arithmetic; digital signal processing chips; mathematics computing; parallel algorithms; parallel architectures; DSP; Fourier analysis; VLSI architecture; arithmetic Fourier transform algorithm; butterfly structure; signal processing; Algorithm design and analysis; Arithmetic; Communication systems; Discrete Fourier transforms; Fourier series; Fourier transforms; Laboratories; Performance analysis; Propulsion; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145490
