A design methodology for fixed-size systolic arrays

The authors present a methodology to design fixed-size systolic arrays. It allows a systematic and hierarchical mapping of full-size arrays to fixed-size arrays. Two processor-clustering techniques are described. They can be used to achieve the following design objectives: (1) transforming inefficient arrays into efficient arrays, (2) reducing the size of an array, (3) reducing the dimension of an array, and (4) balancing local memory and external communication of processors. A technique is described to cluster processors in such a way that the number of I/O pins of the resulting processor is independent of the number of processors that are clustered. The approach presented unifies and generalizes array reduction techniques