DocumentCode

3430628

Title

Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations

Author

Vermaak, H.J. ; Kerkhoff, H.G.

Author_Institution

MESA

fYear

2001

fDate

2001

Firstpage

35

Lastpage

41

Keywords

Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Delay; Electrical fault detection; Fault detection; Flip-flops; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2001. IEEE European

ISSN

1530-1877

Print_ISBN

0-7695-1017-5

Type

conf

DOI

10.1109/ETW.2001.946658

Filename

946658