Title :
Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations
Author :
Vermaak, H.J. ; Kerkhoff, H.G.
Author_Institution :
MESA
Keywords :
Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Delay; Electrical fault detection; Fault detection; Flip-flops; Process design;
Conference_Titel :
Test Workshop, 2001. IEEE European
Print_ISBN :
0-7695-1017-5
DOI :
10.1109/ETW.2001.946658
